“Microelectronics Education at the end of Moore's Law"
Director, Microsystems Technology Office
Defense Advanced Research Projects Agency
Dr. Robert (Bob) Colwell joined the Microsystems Technology Office in April 2011 as the Deputy Director. His interests include architectural and hardware engineering, CPUs, chipsets, buses, memories, and electronics. Before joining DARPA, Dr. Colwell worked as a consultant, specializing in general computer HW/SW, for industry and academia. From 1990 – 2001, Dr. Colwell worked for Intel Corporation and served as Chief Architect (IA32) responsible for all of Intel's Pentium CPU architecture efforts. He also initiated and led Intel's Pentium 4 CPU development. In 1997, Dr. Colwell was named an Intel Fellow, the highest technical grade at the company. As a member of the technical staff at Bell Labs from 1977 to 1980, Dr. Colwell worked on the BellMac series of microprocessors. Dr. Colwell has been a recipient of the Eckert-Mauchly Award for “outstanding achievements in the design and implementation of industry-changing microarchitectures, and for significant contributions to the RISC/CISC architecture debate. In addition, Dr. Colwell was elected to IEEE Fellow and the National Academy of Engineering for “contributions to turning novel computer architecture concepts into viable, cutting-edge commercial processors.” From 2006 – 2009, Dr. Colwell was selected as member of Information Systems Advanced Technology (ISAT) and co-chaired Machine Learning on Multicore in 2009. Having written more than two dozen publications and one book, Dr. Colwell has been an invited speaker by the Department of Defense, Google and multiple universities. He is the inventor/co-inventor on 40 patents and is a recipient of the Carnegie-Mellon Distinguished Alumni Fellows Award and an Alumni Achievement Award from the University of Pittsburgh. Dr. Colwell received a Bachelors of Science, Electrical Engineering from the University of Pittsburgh, and both his Masters of Science, Electrical Engineering and Doctor of Philosophy from Carnegie-Mellon University.
Paul Franzon. Flips, MOOCs, OOCs and Hybrids: The new world of higher education
Paul D. Franzon is currently a Distinguished Alumni Professor of Electrical and Computer Engineering at North Carolina State University. He earned his Ph.D. from the University of Adelaide, Adelaide, Australia in 1988. He has also worked at AT&T Bell Laboratories, DSTO Australia, Australia Telecom and two companies he cofounded, Communica and LightSpin Technologies. His current interests center on the technology and design of complex microsystems incorporating VLSI, MEMS, advanced packaging and nano-electronics. He has lead several major efforts and published over 200 papers in these areas. In 1993 he received an NSF Young Investigators Award, in 2001 was selected to join the NCSU Academy of Outstanding Teachers, in 2003, selected as a Distinguished Alumni Professor, and received the Alcoa Research Award in 2005. He is a Fellow of the IEEE.
David Money Harris and Sarah Harris. Introductory Digital Design and Computer Architecture Curriculum
David Money Harris is a Professor of Engineering and Associate Director of the Engineering Clinic Program at Harvey Mudd College. Dr. Harris received his Ph.D. from Stanford University in 1999 and his S.B. and M. Eng. degrees from MIT in 1994. His research interests include high speed CMOS VLSI design and computer arithmetic. He is the author or coauthor of CMOS VLSI Design: A Circuits and Systems Perspective, Digital Design and Computer Architecture, Logical Effort, Skew-Tolerant Circuit Design, and Afoot and Afield Inland Empire. He holds a dozen patents, has written numerous papers, and has designed chips at Sun Microsystems, Intel, Hewlett-Packard, and Evans & Sutherland.
Alex K. Jones, Iris Bahar, Srinivas Katkoori, Patrick Madden, Diana Marculescu, and Igor Markov. “Scaling” the Impact of EDA Education: Preliminary Findings from the CCC Workshop Series on Extreme Scale Design Automation
Alex K. Jones received the BS degree in 1998 in physics from the College of William and Mary in Williamsburg, Virginia, and the MS and PhD degrees in 2000 and 2002, respectively, in electrical and computer engineering at Northwestern University. He is currently the director of computer engineering and an associate professor of electrical and computer engineering and computer science at the University of Pittsburgh, Pennsylvania. He is a Walter P. Murphy Fellow of Northwestern University. His research interests include compilation techniques for configurable systems and architectures, behavioral and low-power synthesis, parallel architectures and networks, radio frequency identification (RFID), and sensor networks for sustainable systems. He is the author of more than 70 publications in these areas. He has served on several conference program committees in these areas including most recently the program chair for the GLSVLSI conference and is a past program/general chair for the MSE conference. He is currently a senior member of the IEEE and the ACM. He is a recipient of the ACM Distinguished Service Award amongst others
Brucek Khailany. GPU Design in a Power-Limited Era
Brucek Khailany has 16 years of experience designing high-performance power-efficient parallel processors in academic and commercial settings with research interests that span a broad number of topics, including energy-efficient throughput-oriented processor architectures and circuits, software-managed memory and register hierarchies, VLSI design methodology, and computer arithmetic. Most recently, Dr. Khailany joined NVIDIA in December 2009 as a member of the Computer Architecture Research Group. At NVIDIA, he has served in a technical leadership role on the NVIDIA Echelon project for the DARPA Ubiquitous High Performance Computing program and other internal research and product development efforts. Prior to joining NVIDIA, Dr. Khailany was a Co-Founder and Principal Architect at Stream Processors, Inc. (SPI) where he led the design and implementation of highly-parallel programmable processors. From 2004-2009, SPI developed the industry’s first commercially-available stream processor architecture targeting signal and image processing applications. Brucek was responsible for instruction-set architecture, micro-architecture, logic and circuit design, and VLSI design methodology for key processor components. Prior to his position at SPI, Brucek received his Ph.D. and Masters in 2003 and 2000 from Stanford University. At Stanford, he led the silicon implementation of the Imagine stream processor, a research chip that introduced the concepts of stream processing and partitioned register organizations and was a pre-cursor to SPI’s Storm-1 product family. He is a Senior Member of IEEE, a member of ACM, was an Intel foundation fellowship recipient at Stanford, and received BSE’s in Electrical and Computer Engineering from the University of Michigan in 1997.
The majority of our students being educated in microelectronic systems design are headed to industry, especially at the B.S. or M.S. level. The matter of how we take this into account as we educate students is not a new issue, but it needs to be periodically revisited as technology, economics, and even culture change. To help us think anew about student preparation, we have invited experienced engineers in industry to offer their perspectives and have a conversation with us on questions such as the following:
Harald Smit, Sr. Manager for Workstation Performance Tuning and Release Management, NVIDIA Corp.
Rowland Reed, Principal/Manager Engineer QCT DSP Core Design team, Qualcomm Inc.
Brucek Khailany, Computer Architecture Research Group, NVidia
Jim Hamblen, Professor, Computer Systems and Software, Georgia Tech
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